Summary
This report examines and projects the technologies involved, their likely developments, what problems and choices are facing users, and where the opportunities and pitfalls are. The worldwide markets for MCMs, MCPs, SiP, and 3D TSV packages are analyzed and projected.
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Table of Contents
Chapter 1 Introduction 1-1
Chapter 2 Executive Summary 2-1
2.1 Summary of Technology Issues 2-1
2.2 Summary of Market Forecasts 2-7
Chapter 3 Technology Issues and Trends 3-1
3.1 Overview of HDP Technology 3-1
3.1.1 Need for Multiple IC Integration 3-1
3.1.2 Challenges of Multiple IC Integration 3-9
3.1.3 Technical Constraints of Integration 3-10
3.1.4 Economic Benefits of HDP 3-12
3.1.5 Technology Issues 3-16
3.2 2D Packages 3-18
3.2.1 MCMs 3-18
3.2.1.1 Substrates 3-22
3.2.1.2 Thermal Management 3-30
3.2.1.3 Design 3-32
3.2.1.4 Known Good Die 3-36
3.2.2 System In Package (SiP) 3-37
3.2.2.1 SiP Challenges 3-40
3.2.2.2 Cost 3-43
3.2.2.3 SiP Design 3-46
3.2.2.4 SoC Versus SiP 3-47
3.2.3 Multichip Package (MCP) 3-49
3.2.4 Package-On-Package (PoP) 3-51
3.3 2.5D and 3D Packages 3-56
3.3.1 Conventional Wafer Fan-Out Technologies 3-58
3.3.2 Silicon Interposers 3-66
3.3.3 3D-IC Stacks 3-67
Chapter 4 Applications 4-1
4.1 Semiconductor Industry by End Market 4-1
4.2 Memory 4-9
4.2.1 DRAM 4-9
4.2.2 NAND 4-16
4.2.3 China Memory 4-23
4.2.4 HDD vs SSD 4-25
4.3 Foundry Sector 4-31
Chapter 5 Competitive Environment 5-1
5.1 HDP Manufacturers 5-1
Chapter 6 3-D-TSV Technology 6-1
6.1 Driving Forces In 3D-TSV 6-1
6.2 3-D Package Varieties 6-11
6.3 TSV Processes 6-17
6.4 Critical Processing Technologies 6-19
6.4.1 Plasma Etch Technology 6-23
6.4.2 Cu Plating 6-27
6.4.3 Thin Wafer Bonding 6-28
6.4.4 Wafer Thinning/CMP 6-32
6.4.5 Lithography 6-33
6.5 Applications 6-38
6.6 Limitations Of 3-D Packaging Technology 6-44
6.6.1 Thermal Management 6-44
6.6.2 Cost 6-46
6.6.3 Design Complexity 6-47
6.6.4 Time To Delivery 6-52
6.7 Company Profiles 6-53
Chapter 7 Market Forecast 7-1
7.1 Overview of Advanced Packages 7-1
7.2 Driving Forces 7-2
7.3 System-in-Package (SiP) 7-3
7.4 Flip Chip/Wafer Level Packaging 7-10
7.5 Worldwide IC Market Forecast 7-19
7.6 Worldwide Packaging Market Forecast 7-22
7.7 Worldwide Advanced Package Forecast 7-24
7.7.1 Worldwide 3-D Through Silicon Via (TSV) Market 7-34
7.7.1.1 TSMC CoWoS 7-42
7.7.1.2 Intel Foveros 7-48
7.7.1.3 HBM (High Bandwidth Memory) Packages 7-51
7.7.1.4 Chiplets 7-57
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List of Tables/Graphs
List of Tables
3.1 Multichip Modules Vs. Circuit Board Assemblies 3-13
3.2 MCM Cost Comparison 3-15
3.3 Materials Challenge For Packaging 3-17
3.4 Substrate Technology Features 3-25
3.5 Comparison of SoC and SiP Architectures 3-48
3.6 Comparison of CSP and PoP Architectures 3-52
4.1 Global Semiconductor Forecast By End Market 4-5
4.2 Global Semiconductor Revenue Forecast By Device Type 4-7
4.3 Global Semiconductor Unit Forecast By Device Type 4-8
4.4 DRAM Supply 4-10
4.5 DRAM Demand 4-11
4.6 DRAM Revenues 4-13
4.7 NAND Supply 4-17
4.8 NAND Supply-Demand 4-19
4.9 NAND Unit Demand By Application 4-20
4.10 NAND Revenues 4-21
4-11 Comparison Of HDD and SSD For Storage 4-26
4-12 Foundry Market Forecast 4-32
4-13 Comparison Of Foundry Capacities 4-35
5.1 MCM Manufacturers 5-10
6.1 3-D Mass Memory Volume Comparison Between Other Technologies and TI’s 3D Technology In Cm3/Gbit 6-7
6.2 3-D Mass Memory Weight Comparison Between Other Technologies and TI’s 3D Technology In Grams3/Gbit 6-8
7.1 Semiconductor Forecast by Revenues 7-20
7.2 Worldwide IC Package Market Forecast 7-23
7.3 Worldwide Advanced Package Market 7-29
7.4 TSMC’S CoWoS Revenue Analysis 7-49
7.5 HBM TAM Demand 2023-2026 7-56
List of Figures
1.1 Schematic Cross-Section View Of An MCM-D 1-3
1.2 Cross-Section Of The RF And Microwave MCM-D Structure 1-5
1.3 Thin Film Layers On The Planarized Core Layer Of MCM-SL/D Technology 1-8
1.4 Flip Chip MCP 1-11
1.5 SIP Cross Section 1-14
3.1 IC Packaging Trends 3-6
3.2 Technology Tree For HDP Types 3-7
3.3 Form Factor Decrease By Package Type 3-8
3.4 Wafer Level Packaging Processing Line 3-60
3.5 TSMC’s InFO 3-63
3.6 SLIM and SWIFT Package Definition 3-65
4.1 Global Semiconductor Forecast By End Market 4-6
4.2 DRAM Roadmap By Die Shrink 4-15
4.3 3D NAND Roadmap By Die Layers 4-22
4.4 HDD and SSD Shipments Forecast 4-28
4.5 HDD and SSD ASP 4-29
4.6 HDD and SSD Zetabytes 4-30
4.7 Pure-Play Foundry Market Shares 4-34
6.1 3-D Technology On DRAM Density 6-2
6.2 3-D Through-Silicon Via (TSV) 6-5
6.3 Graphical Illustration Of The Silicon Efficiency Between MCMs And 3D Technology 6-9
6.4 Silicon Efficiency Comparison Between 3D Packaging
Technology And Other Conventional Packaging Technologies 6-10
6.5 3D Packages 6-12
6.6 Via First, Middle, And Last Process Flows 6-18
6.7 Via First TSV Process Flow 6-21
6.8 New Applications Driving TSV Growth 6-39
6.9 Projection Of TSV Applications And Process Requirements 6-41
6-10 3-D Technology For DRAM 6-43
6.11 Moore's Law For Active Element Density 6-48
7.1 Various System-In-Package (SiP) Applications 7-4
7.2 SiP Structures 7-7
7.3 Wire Bond Versus Flip Chip 7-15
7.4 Flip Chip And Wire Bond Equipment Forecast 7-16
7.5 Growth In Copper Wire Bonding 7-18
7.6 UNIT SHIPMENTS OF SEMICONDUCTORS 7-21
7.7 WLP Demand By Devices 7-31
7.8 Device Shipment Forecast FIWLP vs FOWLP 7-32
7.9 WLP Demand By Wafers 7-33
7.10 Projection of 3-D TSV Applications And Process Requirement 7-36
7.11 Market Forecast of 3-D TSV Units 7-37
7.12 Market Forecast of 3-D TSV Wafers 7-38
7.13 TSMC’s CoWoS Advanced Package 7-44
7.14 TSMC’s CoWoS Advanced Package Revenues 7-47
7.15 SK hynix HBM3 Package 7-53
