Summary

この調査レポートは、300mm/銅/低誘導率 (Low-k)の統合へ影響を与える技術と経済について解説しています。また300mm ウエハー/ツール、銅沈着/エッチング/CMP、そして低誘導率 (Low-k)材料のタイミング、動向、課題、市場分析を掲載しています。また市場予測も提供しています。

This report discusses the technological and economic impact on the 300mm/Cu/Low-K convergence.  This report discusses the timing, trends, issues, and market analysis of 300mm wafers/tools, copper deposition/etch/CMP, and low-k materials. Markets are analyzed and projected.
 

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Table of Contents

TABLE OF CONTENTS

Chapter 1       Introduction       1-1

Chapter 2       Executive Summary     2-1

2.1      Summary of Technical Issues      2-1
2.2     Summary of Market Forecasts     2-5

Chapter 3     300/450mm Wafer Issues and Trends     3-1

3.1      Introduction      3-1
3.2      Industry Consortia     3-9
3.3     Benefits of 450mm Wafers     3-16
3.4     Requirements For IC Manufacturers     3-23
3.5     Impact on Automation     3-25
3.5.1     Software     3-29
3.6     450mm Wafer Issues     3-31
3.6.1     Overview     3-31
3.6.2     Economic Challenges     3-40

Chapter 4       Copper Issues and Trends     4-1

4.1      Advantages of Copper      4-1
4.2      Copper Processing Challenges     4-7
4.3     Metal Deposition     4-18
4.3.1     Seed Layer     4-18
4.3.2     Bulk Copper Fill     4-21
4.4     Barriers     4-25
4.5     Planarization     4-26
4.6    Metrology    4-30
4.7    Competing against Aluminum Damascene    4-36
4.8    Copper for 22nm    4-38
4.8.1    Low-K and Hard Metal Mask Deposition    4-42
4.8.2    Lithography    4-43
4.8.3    Etch    4-43
4.8.4    Post-etch residue removal    4-45
4.8.5    Chemical mechanical polishing    4-46
4.9    Equipment Suppliers' Copper Electroplating Products    4-48
4.10    Summary    4-56
4.10.1    Advantages/Disadvantages of Cu    4-58
4.10.2    Processing Issues    4-59
4.10.3    Challenges    4-66

Chapter 5    Low-K Dielectric Issues and Trends    5-1

5.1    Introduction    5-1
5.2    Ideal Dielectric    5-2
5.3    Types of Low-K Dielectrics    5-5
5.3.1    FSG    5-5
5.3.2    HSQ    5-7
5.3.3    Nanoporous Silica    5-8
5.3.4    Spin-on Polymers    5-9
5.3.5    BCB    5-17
5.3.6    Flowfill    5-17
5.3.7    CVD    5-18
5.3.8    AF4    5-21
5.3.9    PTFE    5-23
5.4    Processing Issues    5-23
5.5    Summary    5-29
5.5.1    Integration Issues    5-29
5.5.2    Low-K Dielectric Issues    5-30

Chapter 6    Market Analysis    6-1

6.1    Semiconductor Market    6-1
6.2    Road to Recovery    6-3
6.3    Market Forecast Assumptions    6-7
6.4    450mm Wafer Market Forecast    6-8
6.5    300/450mm Equipment Market    6-12
6.5.1    300/450mm Equipment Tools    6-12
6.5.2    Factory Automation in 300mm Fab Market    6-16
6.6    Copper Processing Equipment Market    6-20
6.7    Low-K Dielectric Market    6-29

List of Tables

3.1    Completed Wafer Price Increases With Time And Minimum
Feature Sizes    3-19
3.2    Cost of 450mm Fab    3-24
3.3    Generic Model For CZ Crystal Yield    3-36
5.1    Low-K Material Requirements    5-4
5.2    Low-K Materials    5-6
6.1    Worldwide Market Forecast of Si Wafers    6-9
6.2    Worldwide Market Forecast of 300mm Equipment    6-13
6.3    Process Tool Automation For 300mm Fabs    6-17
6.4    Worldwide Forecast of Automation Transfer Tools    6-18
6.5    Worldwide Forecast of Copper Processing Equipment    6-23
6.6    Worldwide Forecast of Low-K Market    6-30

List of Figures

3.1    Increase in Wafer Diameter With Time    3-2
3.2    R&D Costs For Each Wafer Diameter Introduction    3-6
3.3    Fab Costs For Each Wafer Diameter    3-7
3.4    Revenues For Semiconductor and Semiconductor Equipment    3-8
3.5    ITRS Has Its Roadmap For 450mm Wafers    3-10
3.6    450mm Consortia    3-11
3.7    Completed  Wafer  Price  Increases  With  Time  and  Minimum
Feature Sizes    3-17
3.8    IC Cost With Wafer Size And Device Feature Sizes    3-21
3.9    Trends  In  Manufacturing  Variables  In  The    Transition  From
300m To 450mm Wafers    3-22
3.10    Wafer Thickness Trends With Diameter    3-33
3.11    Polysilicon Usage By The Solar Industry    3-38
3.12    Increasing Cost Of Wafer With Time    3-41
4.1    Reduced Complexity of Copper Interconnect    4-4
4.2    Interconnect Delay for Copper    4-6
4.3    ALD Versus PVD Copper Barrier    4-10
4.4    Copper CMP Steps And Challenges    4-14
4.5    Electromigration Resistance    4-17
4.6    Metal Diffusion Barrier    4-27
4.7    Cu Planarization Process    4-28
4.8    Copper ECMD Process    4-31
4.9    Damascus Complete Copper    4-51
4.10    Copper/Low-K Interconnect Schemes    4-53
4.11    Copper And Low-K Integration Concerns    4-67
5.1    Low-K Roadmap    5-3
6.1    300mm Wafer Market As Percentage of Total Market    6-10
6.2    Forecast of 450mm Processing Equipment    6-14
6.3    Interconnect Technology Requirements    6-21
6.3    Electrochemical Deposition Market Shares -   Revenues    6-24
6.5    Copper Implementation By Geographic Region    6-26
6.6    Copper Implementation By Feature Size    6-27
6.7    Low-K Deposition Market Shares    6-32
6.8    Low-K Precursor Market    6-34